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52
Makefile
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52
Makefile
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# SPDX-License-Identifier: Apache-2.0
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# ******************************************************************************
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#
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# @file Makefile
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#
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# @brief Makefile for PCI Utiliy Functions library
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#
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# @copyright Copyright (C) 2024 Jackrabbit Founders LLC. All rights reserved.
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#
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# @date Mar 2024
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# @author Barrett Edwards <code@jrlabs.io>
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#
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# ******************************************************************************
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CC=gcc
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CFLAGS= -g3 -O0 -Wall -Wextra
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MACROS=
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INCLUDE_DIR=/usr/local/include
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LIB_DIR=/usr/local/lib
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INCLUDE_PATH=-I $(INCLUDE_DIR)
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LIB_PATH=-L $(LIB_DIR)
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LIBS=-l arrayutils
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TARGET=pciutils
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all: lib$(TARGET).a
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lib$(TARGET).a: main.o
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ar rcs $@ $^
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main.o: main.c main.h
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$(CC) -c $< $(CFLAGS) $(MACROS) $(INCLUDE_PATH) -o $@
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clean:
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rm -rf ./*.o ./*.a testbench
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doc:
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doxygen
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install: lib$(TARGET).a
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sudo cp lib$(TARGET).a $(LIB_DIR)/
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sudo cp main.h $(INCLUDE_DIR)/$(TARGET).h
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.PHONY: all clean doc install
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# Variables
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# $^ Will expand to be all the sensitivity list
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# $< Will expand to be the frist file in sensitivity list
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# $@ Will expand to be the target name (the left side of the ":" )
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# -c gcc will compile but not try and link
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main.c
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869
main.c
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/* SPDX-License-Identifier: Apache-2.0 */
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/**
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* @file pcie.c
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*
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* @brief Code file for PCIe Config space operations
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*
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* @copyright Copyright (C) 2024 Jackrabbit Founders LLC. All rights reserved.
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*
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* @date Jan 2024
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* @author Barrett Edwards <code@jrlabs.io>
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*
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*/
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/* INCLUDES ==================================================================*/
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/* printf()
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*/
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#include <stdio.h>
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#include <arrayutils.h>
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#include "pciutils.h"
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/* MACROS ====================================================================*/
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#define MAX_INDENT 32
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/* ENUMERATIONS ==============================================================*/
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/* STRUCTS ===================================================================*/
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/* PROTOTYPES ================================================================*/
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/* GLOBAL VARIABLES ==========================================================*/
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/**
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* String representation of _PCAP
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*
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* These are 8-bit IDs
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*/
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const char *STR_PCAP[] = {
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"PCI Power Management Interface", // 0x01
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"Accelerated Graphics Port", // 0x02
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"Vital Product Data", // 0x03
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"Slot Numbering (for Bridge)", // 0x04
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"Message Signaled Interrupts", // 0x05
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"CompactPCI Hot Swap", // 0x06
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"PCI-X (Deprecated)", // 0x07
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"HyperTransport (Deprecated)", // 0x08
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"Vendor Specific", // 0x09
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"Debug port", // 0x0a
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"CompactPCI central resource control", // 0x0b
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"PCI Hot-Plug (Deprecated)", // 0x0c
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"PCI Bridge Subsystem Vendor ID", // 0x0d
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"AGP 8x (Deprecated)", // 0x0e
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"Secure Device (Deprecated)", // 0x0f
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"PCI Express", // 0x10
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"MSI-X", // 0x11
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"Serial ATA Data/Index Configuration", // 0x12
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"Conventional PCI Advanced Features (AF)", // 0x13
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"Enhanced Allocation", // 0x14
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"Flattening Portal Bridge" // 0x15
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};
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/**
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* String representation of _PCEC
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*
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*/
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const char *STR_PCEC[] = {
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"Advanced Error Reporting", // 0x0001
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"Virtual Channel (VC)", // 0x0002
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"Device Serial Number", // 0x0003
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"Power Budgeting", // 0x0004
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"Root Complex Link Declaration", // 0x0005
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"Root Complex Internal Link Control", // 0x0006
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"Root Complex Event Collector Endpoint Association", // 0x0007
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"Multi-Function Virtual Channel (MFVC)", // 0x0008
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"Virtual Channel (VC)", // 0x0009
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"Root Complex Register Block (RCRB) Header", // 0x000a
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"Vendor-Specific Extended Capability (VSEC)", // 0x000b
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"Access Control Services (ACS)", // 0x000d
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"Alternative Routing-ID Interpretation (ARI)", // 0x000e
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"Address Translation Services (ATS)", // 0x000f
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"Single Root I/O Virtualization (SR-IOV)", // 0x0010
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"Multi-Root I/O Virtualization (MR-IOV) (Deprecated)", // 0x0011
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"Multicast", // 0x0012
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"Page Request Interface (PRI)", // 0x0013
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"Resizable BAR", // 0x0015
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"Dynamic Power Allocation (DPA)", // 0x0016
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"TPH Requester", // 0x0017
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"Latency Tolerance Reporting (LTR)", // 0x0018
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"Secondary PCI Express", // 0x0019
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"Protocol Multiplexing (PMUX)", // 0x001a
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"Process Address Space ID (PASID)", // 0x001b
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"LN Requester (LNR)", // 0x001c
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"Downstream Port Containment (DPC)", // 0x001d
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"L1 PM Substates", // 0x001e
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"Precision Time Measurement (PTM)", // 0x001f
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"PCI Express over M-PHY (M-PCIe)", // 0x0020
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"FRS Queueing", // 0x0021
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"Readiness Time Reporting", // 0x0022
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"Designated Vendor-Specific Extended Capability", // 0x0023
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"VF Resizable BAR", // 0x0024
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"Data Link Feature", // 0x0025
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"Physical Layer 16.0 GT/s", // 0x0026
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"Lane Margining at the Receiver", // 0x0027
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"Hierarchy ID", // 0x0028
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"Native PCIe Enclosure Management (NPEM)", // 0x0029
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"Physical Layer 32.0 GT/s", // 0x002A
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"Alternate Protocol", // 0x002B
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"System Firmware Intermediary (SFI)", // 0x002C
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"Shadow Functions", // 0x002D
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"Data Object Exchange", // 0x002E
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"Device 3", // 0x002F
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"Integrity and Data Encryption (IDE)", // 0x0030
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"Physical Layer 64.0 GT/s Capability", // 0x0031
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"Flit Logging", // 0x0032
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"Flit Performance Measurement", // 0x0033
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"Flit Error Injection" // 0x0034
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};
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/**
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* String representation of PCI Sub Class Code for Memory Controllers (MC)
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*
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* Class Code 0x05
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*/
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const char *STR_PCMC[] =
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{
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"Ram", // 0x00
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"Flash", // 0x01
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"CXL Memory", // 0x02
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"Other Memory", // 0x80
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};
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/**
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* String representations of PCI Programming Interface for Sub Class: CXL memory (CX)
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*
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* Class Code: 0x05
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* Sub Class code 0x02
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*/
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const char *STR_PCCX[] =
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{
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"Vendor Specific Interface)", // 0x00
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"CXL 2.0 or later" // 0x01
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};
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/**
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* String representation of PCI Sub Class Code for Mass Storage Controllers (MS)
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*
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* Class Code 0x01
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*/
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const char *STR_PCMS[] =
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{
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"SCSI Device or Controller", // 0x00
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"IDE Controller", // 0x01
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"Floppy Disk Controller - Vendor Specific Interface", // 0x02
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"IPI Bus Controller - Vendor Specific Interface", // 0x03
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"RAID Controller - Vendor Specific Interface", // 0x04
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"ATA Controller", // 0x05
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"SATA Controller", // 0x06
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"SAS Controller", // 0x07
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"Non-Volatile Memory Subsystem", // 0x08
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"Universal Flash Storage Controller", // 0x09
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"Other Mass storage Controller" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Network Controllers (NC)
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*
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* Class Code 0x02
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*/
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const char *STR_PCNC[] =
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{
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"Ethernet Controller", // 0x00
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"Token Ring Controller", // 0x01
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"FDDI Controller", // 0x02
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"ATM Controller", // 0x03
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"ISDN Controller", // 0x04
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"WorldFip Controller", // 0x05
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"PICMG", // 0x06
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"InfiniBand Controller", // 0x07
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"Host fabric Controller - Vendor Specific", // 0x08
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"Other Network Controller" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Dispaly Controllers (DC)
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*
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* Class Code 0x03
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*/
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const char *STR_PCDC[] =
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{
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"VGA Compatible Controller", // 0x00
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"XGA Controller", // 0x01
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"3D Controller", // 0x02
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"Other Controller" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Multimedia Controllers (UC)
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*
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* Class Code 0x04
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*/
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const char *STR_PCUC[] =
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{
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"Video Device", // 0x00
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"Audio Device", // 0x01
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"Computer Telephone Device", // 0x02
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"HD Audio Device", // 0x03
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"Other Multimedia device", // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Bridge Devices (BD)
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*
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* Class Code 0x06
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*/
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const char *STR_PCBD[] =
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{
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"Host Bridge", // 0x00
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"ISA Bridge", // 0x01
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"EISA", // 0x02
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"MCA", // 0x03
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"PCI-to-PCI Bridge", // 0x04
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"PCMCIA Bridge", // 0x05
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"NuBus Bridge", // 0x06
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"CardBus Bridge", // 0x07
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"RaceWay Bridge", // 0x08
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"Semi-Transparent Bridge", // 0x09
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"InfiniBand to PCI Host Bridge", // 0x0A
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"Advanced Switching to PCI Host Bridge", // 0x0B
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"Other Bridge", // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Simple Communication Controllers (SC)
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*
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* Class Code 0x07
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*/
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const char *STR_PCSC[] =
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{
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"Generic XT Compatible Serial Controller", // 0x00
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"Parallel Port", // 0x01
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"Multi Port Serial Controller", // 0x02
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"Generic Modem", // 0x03
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"GPIB Controller", // 0x04
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"SMART Card", // 0x05
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"Other Communcations Device" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Generic System Peripherals (SP)
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*
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* Class Code 0x08
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*/
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const char *STR_PCSP[] =
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{
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"Programmable Interrupt Controller", // 0x00
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"DMA Controller", // 0x01
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"System Timer", // 0x02
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"Generic Real Time Clock (RTC) Controller", // 0x03
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"Generic PCI Hot Plug Contoller", // 0x04
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"SD Host Controller", // 0x05
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"IOMMU", // 0x06
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"Root Complex Event Collector", // 0x07
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"Other System Peripheral" // 0x08
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};
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/**
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* String representaton of PCI Sub Class Code for Input Device (ID)
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*
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* Class Code 0x09
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*/
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const char *STR_PCID[] =
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{
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"Keyboard Controller", // 0x00
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"Digitizer (pen)", // 0x01
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"Mouse Controller", // 0x02
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"Scanner Controller", // 0x03
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"Gameport Controller", // 0x04
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"Other Controller" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Docking Stations (DS)
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*
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* Class Code 0x0A
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*/
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const char *STR_PCDS[] =
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{
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"Generic Docking Station", // 0x00
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"Other type of Docking Station", // 0x01
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};
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/**
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* PCI Sub Class Code for Processors (PR)
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*
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* Class Code 0x0B
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*/
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const char *STR_PCPR[] =
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{
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"386", // 0x00
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"486", // 0x01
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"Pentium", // 0x02
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"Alpha", // 0x10
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"PowerPC", // 0x20
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"MIPS", // 0x30
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"Co-Processor", // 0x40
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"Other Processor" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Serial Bus Controllers (SB)
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*
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* Class Code 0x0C
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*/
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const char *STR_PCSB[] =
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{
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"Firewire", // 0x00
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"ACCESS.bus", // 0x01
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"SSA", // 0x02
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"USB", // 0x03
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"Fibre Channel", // 0x04
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"SM Bus", // 0x05
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"Infiniband (Depricated)", // 0x06
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"IPMI", // 0x07
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"SERCOS", // 0x08
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"CANbus", // 0x09
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"MIPI I3C Controller", // 0x0A
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"OTher Controller" // 0x80
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};
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/**
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* String representation of PCI Sub Class Code for Wireless Controllers (WC)
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*
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* Class Code 0x0D
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*/
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const char *STR_PCWC[] =
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{
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"iRDA Compatible Controller", // 0x00
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"IR Controller", // 0x01
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"RF Controller", // 0x10
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"Bluetooth", // 0x11
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"Broadband", // 0x12
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"Ethernet 5 GHz", // 0x20
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"Ethernet 2.4 GHz", // 0x21
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"Cellular Controller / Modem", // 0x40
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"Cellular Controller + Ethrenet", // 0x41
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"Other Wireless Controller", // 0x80
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String representation of PCI Sub Class Code for Intelligent IO Controllers (IO)
|
||||||
|
*
|
||||||
|
* Class Code 0x0E
|
||||||
|
*/
|
||||||
|
const char *STR_PCIO[] =
|
||||||
|
{
|
||||||
|
"Intelligent IO", // 0x00
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String represenation of PCI Sub Class Code for Satellite Controllers (SA)
|
||||||
|
*
|
||||||
|
* Class Code 0x0F
|
||||||
|
*/
|
||||||
|
const char *STR_PCSA[] =
|
||||||
|
{
|
||||||
|
"TV", // 0x01
|
||||||
|
"Audio", // 0x02
|
||||||
|
"Voice", // 0x03
|
||||||
|
"Data", // 0x04
|
||||||
|
"Other" // 0x80
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String representation of PCI Sub Class Code for Encryption Controllers (EN)
|
||||||
|
*
|
||||||
|
* Class Code 0x10
|
||||||
|
*/
|
||||||
|
const char *STR_PCEN[] =
|
||||||
|
{
|
||||||
|
"Network and Computing Encryption Decryption controller", // 0x00
|
||||||
|
"Entertainment encryption and decryption controller", // 0x10
|
||||||
|
"Other encryption and decryption controller", // 0x80
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String representation of PCI Sub Class Code for Data Acquisition and Signal Processing Controllers (DA)
|
||||||
|
*
|
||||||
|
* Class Code 0x11
|
||||||
|
*/
|
||||||
|
const char *STR_PCDA[] =
|
||||||
|
{
|
||||||
|
"DPIO Modules", // 0x00
|
||||||
|
"Performance Counters", // 0x01
|
||||||
|
"Communications synchronization", // 0x10
|
||||||
|
"Management Card", // 0x20
|
||||||
|
"Other data acquisition controller" // 0x80
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String representation of PCI Sub Class Code for Processing Accelerators (PA)
|
||||||
|
*
|
||||||
|
* Class Code 0x12
|
||||||
|
*/
|
||||||
|
const char *STR_PCPA[] =
|
||||||
|
{
|
||||||
|
"Processing Accelerator - Vendor Specific Interface", // 0x00
|
||||||
|
"SNIA Smart Data Acceleration Interface (SDXI)", // 0x00
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* String representation of PCI Sub Class Code for Non Essential Instrumentation (NE)
|
||||||
|
*
|
||||||
|
* Class Code 0x13
|
||||||
|
*/
|
||||||
|
const char *STR_PCNE[] =
|
||||||
|
{
|
||||||
|
"Non Essential Instrumentation - Vendor Specific Interface", // 0x00
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* FUNCTIONS =================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCAP
|
||||||
|
*/
|
||||||
|
const char *pcap(unsigned u)
|
||||||
|
{
|
||||||
|
if (u >= PCAP_MAX)
|
||||||
|
return NULL;
|
||||||
|
return STR_PCAP[u];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCCX
|
||||||
|
*/
|
||||||
|
const char *pccx(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCCX_VS: return STR_PCCX[0];
|
||||||
|
case PCCX_CXL2_0: return STR_PCCX[1];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
|
||||||
|
* Return a string representation of enumeration _PCEC
|
||||||
|
*/
|
||||||
|
const char *pcec(unsigned u)
|
||||||
|
{
|
||||||
|
if (u >= PCEC_MAX)
|
||||||
|
return NULL;
|
||||||
|
return STR_PCEC[u];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCMC
|
||||||
|
*/
|
||||||
|
const char *pcmc(unsigned u)
|
||||||
|
{
|
||||||
|
switch(u)
|
||||||
|
{
|
||||||
|
case PCMC_RAM: return STR_PCMC[0];
|
||||||
|
case PCMC_FLASH: return STR_PCMC[1];
|
||||||
|
case PCMC_CXL_MEM: return STR_PCMC[2];
|
||||||
|
case PCMC_OTHER: return STR_PCMC[3];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCMS
|
||||||
|
*/
|
||||||
|
const char *pcms(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCMS_SCSI: return STR_PCMS[0];
|
||||||
|
case PCMS_IDE: return STR_PCMS[1];
|
||||||
|
case PCMS_FLOPPY: return STR_PCMS[2];
|
||||||
|
case PCMS_IPI: return STR_PCMS[3];
|
||||||
|
case PCMS_RAID: return STR_PCMS[4];
|
||||||
|
case PCMS_ATA: return STR_PCMS[5];
|
||||||
|
case PCMS_SATA: return STR_PCMS[6];
|
||||||
|
case PCMS_SAS: return STR_PCMS[7];
|
||||||
|
case PCMS_NVM: return STR_PCMS[8];
|
||||||
|
case PCMS_UFS: return STR_PCMS[9];
|
||||||
|
case PCMS_OTHER: return STR_PCMS[10];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCNC
|
||||||
|
*/
|
||||||
|
const char *pcnc(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCNC_ETH: return STR_PCNC[0];
|
||||||
|
case PCNC_TOKEN: return STR_PCNC[1];
|
||||||
|
case PCNC_FDDI: return STR_PCNC[2];
|
||||||
|
case PCNC_ATM: return STR_PCNC[3];
|
||||||
|
case PCNC_ISDN: return STR_PCNC[4];
|
||||||
|
case PCNC_WORLDFIP: return STR_PCNC[5];
|
||||||
|
case PCNC_PICMG: return STR_PCNC[6];
|
||||||
|
case PCNC_IB: return STR_PCNC[7];
|
||||||
|
case PCNC_HFC: return STR_PCNC[8];
|
||||||
|
case PCNC_OTHER: return STR_PCNC[9];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCDC
|
||||||
|
*/
|
||||||
|
const char *pcdc(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCDC_VGA: return STR_PCDC[0];
|
||||||
|
case PCDC_XGA: return STR_PCDC[1];
|
||||||
|
case PCDC_3D: return STR_PCDC[2];
|
||||||
|
case PCDC_OTHER: return STR_PCDC[3];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCUC
|
||||||
|
*/
|
||||||
|
const char *pcuc(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCUC_VIDEO: return STR_PCUC[0];
|
||||||
|
case PCUC_AUDIO: return STR_PCUC[1];
|
||||||
|
case PCUC_TELEPHONE: return STR_PCUC[2];
|
||||||
|
case PCUC_HD_AUDIO: return STR_PCUC[3];
|
||||||
|
case PCUC_OTHER: return STR_PCUC[4];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCBD
|
||||||
|
*/
|
||||||
|
const char *pcbd(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCBD_HOST: return STR_PCBD[0];
|
||||||
|
case PCBD_ISA: return STR_PCBD[1];
|
||||||
|
case PCBD_EISA: return STR_PCBD[2];
|
||||||
|
case PCBD_MCA: return STR_PCBD[3];
|
||||||
|
case PCBD_PPB: return STR_PCBD[4];
|
||||||
|
case PCBD_PCMCIA: return STR_PCBD[5];
|
||||||
|
case PCBD_NUBUS: return STR_PCBD[6];
|
||||||
|
case PCBD_CARDBUS: return STR_PCBD[7];
|
||||||
|
case PCBD_RACEWAY: return STR_PCBD[8];
|
||||||
|
case PCBD_STPPB: return STR_PCBD[9];
|
||||||
|
case PCBD_IB_PCI: return STR_PCBD[10];
|
||||||
|
case PCBD_AS_PCI: return STR_PCBD[11];
|
||||||
|
case PCBD_OTHER: return STR_PCBD[12];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCSC
|
||||||
|
*/
|
||||||
|
const char *pcsc(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCSC_GENERIC_XT: return STR_PCBD[0];
|
||||||
|
case PCSC_PARALLEL: return STR_PCBD[1];
|
||||||
|
case PCSC_MP_SERIAL: return STR_PCBD[2];
|
||||||
|
case PCSC_MODEM: return STR_PCBD[3];
|
||||||
|
case PCSC_GPIB: return STR_PCBD[4];
|
||||||
|
case PCSC_SMRT_CARD: return STR_PCBD[5];
|
||||||
|
case PCSC_OTHER: return STR_PCBD[6];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCSP
|
||||||
|
*/
|
||||||
|
const char *pcsp(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCSP_PCI: return STR_PCSP[0];
|
||||||
|
case PCSP_DMA: return STR_PCSP[1];
|
||||||
|
case PCSP_TIMER: return STR_PCSP[2];
|
||||||
|
case PCSP_RTC: return STR_PCSP[3];
|
||||||
|
case PCSP_HOT_PLUG: return STR_PCSP[4];
|
||||||
|
case PCSP_SD: return STR_PCSP[5];
|
||||||
|
case PCSP_IOMMU: return STR_PCSP[6];
|
||||||
|
case PCSP_RCEC: return STR_PCSP[7];
|
||||||
|
case PCSP_OTHER: return STR_PCSP[8];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCID
|
||||||
|
*/
|
||||||
|
const char *pcid(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCID_KEYBOARD: return STR_PCID[0];
|
||||||
|
case PCID_PEN: return STR_PCID[1];
|
||||||
|
case PCID_MOUSE: return STR_PCID[2];
|
||||||
|
case PCID_SCANNER: return STR_PCID[3];
|
||||||
|
case PCID_GAME: return STR_PCID[4];
|
||||||
|
case PCID_OTHER: return STR_PCID[5];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCDS
|
||||||
|
*/
|
||||||
|
const char *pcds(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCDS_GENERIC: return STR_PCDS[0];
|
||||||
|
case PCDS_OTHER: return STR_PCDS[1];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCPR
|
||||||
|
*/
|
||||||
|
const char *pcpr(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCPR_386: return STR_PCPR[0];
|
||||||
|
case PCPR_486: return STR_PCPR[1];
|
||||||
|
case PCPR_PENTIUM: return STR_PCPR[2];
|
||||||
|
case PCPR_ALPHA: return STR_PCPR[3];
|
||||||
|
case PCPR_POWERPC: return STR_PCPR[4];
|
||||||
|
case PCPR_MIPS: return STR_PCPR[5];
|
||||||
|
case PCPR_COPROCESSOR: return STR_PCPR[6];
|
||||||
|
case PCPR_OTHER: return STR_PCPR[7];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCSB
|
||||||
|
*/
|
||||||
|
const char *pcsb(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCSB_FIREWIRE: return STR_PCSB[0];
|
||||||
|
case PCSB_ACCESS: return STR_PCSB[1];
|
||||||
|
case PCSB_SSA: return STR_PCSB[2];
|
||||||
|
case PCSB_USB: return STR_PCSB[3];
|
||||||
|
case PCSB_FC: return STR_PCSB[4];
|
||||||
|
case PCSB_SMBUS: return STR_PCSB[5];
|
||||||
|
case PCSB_IB: return STR_PCSB[6];
|
||||||
|
case PCSB_IPMI: return STR_PCSB[7];
|
||||||
|
case PCSB_SERCOS: return STR_PCSB[8];
|
||||||
|
case PCSB_CANBUS: return STR_PCSB[9];
|
||||||
|
case PCSB_I3C: return STR_PCSB[10];
|
||||||
|
case PCSB_OTHER: return STR_PCSB[11];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCWC
|
||||||
|
*/
|
||||||
|
const char *pcwc(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCWC_IRDA: return STR_PCWC[0];
|
||||||
|
case PCWC_IR: return STR_PCWC[1];
|
||||||
|
case PCWC_RF: return STR_PCWC[2];
|
||||||
|
case PCWC_BT: return STR_PCWC[3];
|
||||||
|
case PCWC_BROADBAND: return STR_PCWC[4];
|
||||||
|
case PCWC_ETH5G: return STR_PCWC[5];
|
||||||
|
case PCWC_ETH2_4G: return STR_PCWC[6];
|
||||||
|
case PCWC_CELL: return STR_PCWC[7];
|
||||||
|
case PCWC_CELL_ETH: return STR_PCWC[8];
|
||||||
|
case PCWC_OTHER: return STR_PCWC[9];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCIO
|
||||||
|
*/
|
||||||
|
const char *pcio(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCIO_I2O: return STR_PCIO[0];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCSA
|
||||||
|
*/
|
||||||
|
const char *pcsa(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCSA_TV: return STR_PCSA[0];
|
||||||
|
case PCSA_AUDIO: return STR_PCSA[1];
|
||||||
|
case PCSA_VOICE: return STR_PCSA[2];
|
||||||
|
case PCSA_DATA: return STR_PCSA[3];
|
||||||
|
case PCSA_OTHER: return STR_PCSA[4];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCEN
|
||||||
|
*/
|
||||||
|
const char *pcen(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCEN_NET: return STR_PCEN[0];
|
||||||
|
case PCEN_ENT: return STR_PCEN[1];
|
||||||
|
case PCEN_OTHER: return STR_PCEN[2];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCDA
|
||||||
|
*/
|
||||||
|
const char *pcda(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCDA_DPIO: return STR_PCDA[0];
|
||||||
|
case PCDA_PERF: return STR_PCDA[1];
|
||||||
|
case PCDA_SYNC: return STR_PCDA[2];
|
||||||
|
case PCDA_MGMT: return STR_PCDA[3];
|
||||||
|
case PCDA_OTHER: return STR_PCDA[4];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCPA
|
||||||
|
*/
|
||||||
|
const char *pcpa(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCPA_ACCEL: return STR_PCPA[0];
|
||||||
|
case PCPA_SDXI: return STR_PCPA[1];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return a string representation of enumeration _PCNE
|
||||||
|
*/
|
||||||
|
const char *pcne(unsigned u)
|
||||||
|
{
|
||||||
|
switch (u)
|
||||||
|
{
|
||||||
|
case PCNE_INST: return STR_PCNE[0];
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Print the PCIe Config space
|
||||||
|
*
|
||||||
|
* @param cfgspace __u8* to a buffer with the PCIe cfg space
|
||||||
|
* @param indent The number of spaces to indent
|
||||||
|
*/
|
||||||
|
void pcie_prnt_cfgspace(__u8 *cfgspace, unsigned indent)
|
||||||
|
{
|
||||||
|
struct pcie_cfg_hdr *ph;
|
||||||
|
char space[MAX_INDENT] = " ";
|
||||||
|
|
||||||
|
if (cfgspace == NULL)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (indent >= MAX_INDENT)
|
||||||
|
indent = MAX_INDENT;
|
||||||
|
space[indent] = 0;
|
||||||
|
|
||||||
|
ph = (struct pcie_cfg_hdr*) cfgspace;
|
||||||
|
|
||||||
|
printf("%sPCIe Config Space HDR:\n", space);
|
||||||
|
|
||||||
|
if ( (indent + 2) < MAX_INDENT)
|
||||||
|
{
|
||||||
|
space[indent] = ' ';
|
||||||
|
space[indent+2] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("%sVendor ID 0x%04x\n", space, ph->vendor);
|
||||||
|
printf("%sDevice ID 0x%04x\n", space, ph->device);
|
||||||
|
printf("%sCommand 0x%04x\n", space, ph->command);
|
||||||
|
printf("%sStatus 0x%04x\n", space, ph->status);
|
||||||
|
printf("%sRevision ID 0x%02x\n", space, ph->rev);
|
||||||
|
printf("%sProgramming Interface 0x%02x\n", space, ph->pi);
|
||||||
|
printf("%sSub Class 0x%02x\n", space, ph->subclass);
|
||||||
|
printf("%sBase Class 0x%02x\n", space, ph->baseclass);
|
||||||
|
printf("%sCache Line Size 0x%02x\n", space, ph->cls);
|
||||||
|
printf("%sLatency Timer 0x%02x\n", space, ph->timer);
|
||||||
|
printf("%sHeader Type 0x%02x\n", space, ph->type);
|
||||||
|
printf("%sBIST 0x%02x\n", space, ph->bist);
|
||||||
|
printf("%sBAR0 0x%08x\n", space, ph->bar0);
|
||||||
|
printf("%sBAR1 0x%08x\n", space, ph->bar1);
|
||||||
|
printf("%sBAR2 0x%08x\n", space, ph->bar2);
|
||||||
|
printf("%sBAR3 0x%08x\n", space, ph->bar3);
|
||||||
|
printf("%sBAR4 0x%08x\n", space, ph->bar4);
|
||||||
|
printf("%sBAR5 0x%08x\n", space, ph->bar5);
|
||||||
|
printf("%sCardbus CIS Ptr 0x%08x\n", space, ph->cis);
|
||||||
|
printf("%sSubsystem Vendor ID 0x%04x\n", space, ph->subvendor);
|
||||||
|
printf("%sSubsystem Device ID 0x%04x\n", space, ph->subsystem);
|
||||||
|
printf("%sExpansion ROM Addr 0x%08x\n", space, ph->rom);
|
||||||
|
printf("%sCapabilities Ptr 0x%02x\n", space, ph->cap);
|
||||||
|
printf("%sInterrupt Line %u\n", space, ph->intline);
|
||||||
|
printf("%sInterrupt Pin %u\n", space, ph->intpin);
|
||||||
|
printf("%sMinimum Grant %u\n", space, ph->mingnt);
|
||||||
|
printf("%sMaximum Latency %u\n", space, ph->maxlat);
|
||||||
|
}
|
||||||
|
|
||||||
739
main.h
Normal file
739
main.h
Normal file
@ -0,0 +1,739 @@
|
|||||||
|
/* SPDX-License-Identifier: Apache-2.0 */
|
||||||
|
/**
|
||||||
|
* @file pcie.h
|
||||||
|
*
|
||||||
|
* @brief Header file for PCIe Config Space representation and operations
|
||||||
|
*
|
||||||
|
* @copyright Copyright (C) 2024 Jackrabbit Founders LLC. All rights reserved.
|
||||||
|
*
|
||||||
|
* @date Jan 2024
|
||||||
|
* @author Barrett Edwards <code@jrlabs.io>
|
||||||
|
*
|
||||||
|
* Macro / Enumeration Prefixes (PC)
|
||||||
|
* PCAP - PCI Capabilities Registers (AP)
|
||||||
|
* PCBC - PCI Class Codes (BC)
|
||||||
|
* PCBD - PCI Sub Class Code for Bridge Devices (BD)
|
||||||
|
* PCCX - PCI Programming Interface for Sub Class: CXL memory (CX)
|
||||||
|
* PCDC - PCI Sub Class Code for Dispaly Controllers (DC)
|
||||||
|
* PCDS - PCI Sub Class Code for Docking Stations (DS)
|
||||||
|
* PCEC - PCI Extended Capabilities Registers - (EC)
|
||||||
|
* PCEN - PCI Sub Class Code for Encruyption Controllers (EN)
|
||||||
|
* PCID - PCI Sub Class Code for Input Device (ID)
|
||||||
|
* PCIO - PCI Sub Class Code for Intelligent IO Controllers (IO)
|
||||||
|
* PCMC - PCI Sub Class Code for Memory Controllers (MC)
|
||||||
|
* PCMS - PCI Sub Class Code for Mass Storage Controllers (MS)
|
||||||
|
* PCNC - PCI Sub Class Code for Network Controllers (NC)
|
||||||
|
* PCNE - PCI Sub Class Code for Non Essential Instrumentation (NE)
|
||||||
|
* PCPR - PCI Sub Class Code for Processors (PR)
|
||||||
|
* PCSA - PCI Sub Class Code for Satellite Controllers (SA)
|
||||||
|
* PCSB - PCI Sub Class Code for Serial Bus Controllers (SB)
|
||||||
|
* PCSC - PCI Sub Class Code for Simple communication controllers (SC)
|
||||||
|
* PCSP - PCI Sub Class Code for Generic System Peripherals (SP)
|
||||||
|
* PCUC - PCI Sub Class Code for Multimedia Controllers (UC)
|
||||||
|
* PCWC - PCI Sub Class Code for Wireless Controllers (WC)
|
||||||
|
*/
|
||||||
|
#ifndef _PCIE_H
|
||||||
|
#define _PCIE_H
|
||||||
|
|
||||||
|
/* INCLUDES ==================================================================*/
|
||||||
|
|
||||||
|
/* __u8
|
||||||
|
* __u16
|
||||||
|
*/
|
||||||
|
#include <linux/types.h>
|
||||||
|
|
||||||
|
/* MACROS ====================================================================*/
|
||||||
|
|
||||||
|
#define PCLN_CFG 4096
|
||||||
|
#define PCLN_HDR 64
|
||||||
|
|
||||||
|
/* ENUMERATIONS ==============================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Capabilities Registers (AP)
|
||||||
|
*
|
||||||
|
* These are 8-bit IDs
|
||||||
|
*/
|
||||||
|
enum _PCAP
|
||||||
|
{
|
||||||
|
PCAP_PM = 0x01, //!< PCI Power Management Interface
|
||||||
|
PCAP_AGP = 0x02, //!< Accelerated Graphics Port
|
||||||
|
PCAP_VPD = 0x03, //!< Vital Product Data
|
||||||
|
PCAP_SLOTID = 0x04, //!< Slot Numbering (for Bridge)
|
||||||
|
PCAP_MSI = 0x05, //!< Message Signaled Interrupts
|
||||||
|
PCAP_CHSWP = 0x06, //!< CompactPCI Hot Swap
|
||||||
|
PCAP_PCIX = 0x07, //!< PCI-X (Deprecated)
|
||||||
|
PCAP_HT = 0x08, //!< HyperTransport (Deprecated)
|
||||||
|
PCAP_VNDR = 0x09, //!< Vendor Specific
|
||||||
|
PCAP_DBG = 0x0a, //!< Debug port
|
||||||
|
PCAP_CCRC = 0x0b, //!< CompactPCI central resource control
|
||||||
|
PCAP_HOTPLUG = 0x0c, //!< PCI Hot-Plug (Deprecated)
|
||||||
|
PCAP_SSVID = 0x0d, //!< PCI Bridge Subsystem Vendor ID
|
||||||
|
PCAP_AGP3 = 0x0e, //!< AGP 8x (Deprecated)
|
||||||
|
PCAP_SECURE = 0x0f, //!< Secure Device (Deprecated)
|
||||||
|
PCAP_EXP = 0x10, //!< PCI Express
|
||||||
|
PCAP_MSIX = 0x11, //!< MSI-X
|
||||||
|
PCAP_SATA = 0x12, //!< Serial ATA Data/Index Configuration
|
||||||
|
PCAP_AF = 0x13, //!< Conventional PCI Advanced Features (AF)
|
||||||
|
PCAP_EA = 0x14, //!< Enhanced Allocation
|
||||||
|
PCAP_FPB = 0x15, //!< Flattening Portal Bridge
|
||||||
|
PCAP_MAX
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Extended Capabilities Registers - (EC)
|
||||||
|
*
|
||||||
|
* These are 16-bit IDs
|
||||||
|
*/
|
||||||
|
enum _PCEC
|
||||||
|
{
|
||||||
|
PCEC_AER = 0x0001, //!< Advanced Error Reporting
|
||||||
|
PCEC_VC = 0x0002, //!< Virtual Channel (VC)
|
||||||
|
PCEC_DSN = 0x0003, //!< Device Serial Number
|
||||||
|
PCEC_PB = 0x0004, //!< Power Budgeting
|
||||||
|
PCEC_RCLINK = 0x0005, //!< Root Complex Link Declaration
|
||||||
|
PCEC_RCILINK = 0x0006, //!< Root Complex Internal Link Control
|
||||||
|
PCEC_RCECOLL = 0x0007, //!< Root Complex Event Collector Endpoint Association
|
||||||
|
PCEC_MFVC = 0x0008, //!< Multi-Function Virtual Channel (MFVC)
|
||||||
|
PCEC_VC2 = 0x0009, //!< Virtual Channel (VC)
|
||||||
|
PCEC_RBCB = 0x000a, //!< Root Complex Register Block (RCRB) Header
|
||||||
|
PCEC_VNDR = 0x000b, //!< Vendor-Specific Extended Capability (VSEC)
|
||||||
|
PCEC_ACS = 0x000d, //!< Access Control Services (ACS)
|
||||||
|
PCEC_ARI = 0x000e, //!< Alternative Routing-ID Interpretation (ARI)
|
||||||
|
PCEC_ATS = 0x000f, //!< Address Translation Services (ATS)
|
||||||
|
PCEC_SRIOV = 0x0010, //!< Single Root I/O Virtualization (SR-IOV)
|
||||||
|
PCEC_MRIOV = 0x0011, //!< Multi-Root I/O Virtualization (MR-IOV) (Deprecated)
|
||||||
|
PCEC_MCAST = 0x0012, //!< Multicast
|
||||||
|
PCEC_PRI = 0x0013, //!< Page Request Interface (PRI)
|
||||||
|
PCEC_REBAR = 0x0015, //!< Resizable BAR
|
||||||
|
PCEC_DPA = 0x0016, //!< Dynamic Power Allocation (DPA)
|
||||||
|
PCEC_TPH = 0x0017, //!< TPH Requester
|
||||||
|
PCEC_LTR = 0x0018, //!< Latency Tolerance Reporting (LTR)
|
||||||
|
PCEC_SECPCI = 0x0019, //!< Secondary PCI Express
|
||||||
|
PCEC_PMUX = 0x001a, //!< Protocol Multiplexing (PMUX)
|
||||||
|
PCEC_PASID = 0x001b, //!< Process Address Space ID (PASID)
|
||||||
|
PCEC_LNR = 0x001c, //!< LN Requester (LNR)
|
||||||
|
PCEC_DPC = 0x001d, //!< Downstream Port Containment (DPC)
|
||||||
|
PCEC_L1PM = 0x001e, //!< L1 PM Substates
|
||||||
|
PCEC_PTM = 0x001f, //!< Precision Time Measurement (PTM)
|
||||||
|
PCEC_M_PCIE = 0x0020, //!< PCI Express over M-PHY (M-PCIe)
|
||||||
|
PCEC_FRS = 0x0021, //!< FRS Queueing
|
||||||
|
PCEC_RTR = 0x0022, //!< Readiness Time Reporting
|
||||||
|
PCEC_DVSEC = 0x0023, //!< Designated Vendor-Specific Extended Capability
|
||||||
|
PCEC_VF_REBAR = 0x0024, //!< VF Resizable BAR
|
||||||
|
PCEC_DLNK = 0x0025, //!< Data Link Feature
|
||||||
|
PCEC_16GT = 0x0026, //!< Physical Layer 16.0 GT/s
|
||||||
|
PCEC_LMR = 0x0027, //!< Lane Margining at the Receiver
|
||||||
|
PCEC_HIER_ID = 0x0028, //!< Hierarchy ID
|
||||||
|
PCEC_NPEM = 0x0029, //!< Native PCIe Enclosure Management (NPEM)
|
||||||
|
PCEC_PL = 0x002A, //!< Physical Layer 32.0 GT/s
|
||||||
|
PCEC_AP = 0x002B, //!< Alternate Protocol
|
||||||
|
PCEC_SFI = 0x002C, //!< System Firmware Intermediary (SFI)
|
||||||
|
PCEC_SFUNC = 0x002D, //!< Shadow Functions
|
||||||
|
PCEC_DOE = 0x002E, //!< Data Object Exchange
|
||||||
|
PCEC_DEV3 = 0x002F, //!< Device 3
|
||||||
|
PCEC_IDE = 0x0030, //!< Integrity and Data Encryption (IDE)
|
||||||
|
PCEC_64GT = 0x0031, //!< Physical Layer 64.0 GT/s Capability
|
||||||
|
PCEC_FLITLOG = 0x0032, //!< Flit Logging
|
||||||
|
PCEC_FLITPERF = 0x0033, //!< Flit Performance Measurement
|
||||||
|
PCEC_FLITEI = 0x0034, //!< Flit Error Injection
|
||||||
|
|
||||||
|
PCEC_MAX
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Class Codes (BC)
|
||||||
|
*/
|
||||||
|
enum _PCBC
|
||||||
|
{
|
||||||
|
PCBC_NULL = 0x01, //!<
|
||||||
|
PCBC_MSC = 0x02, //!< Mass Storage Controller
|
||||||
|
PCBC_NET = 0x02, //!< Network controller
|
||||||
|
PCBC_DISPLAY = 0x03, //!< Display controller
|
||||||
|
PCBC_MULTIMEDIA = 0x04, //!< Multimedia device
|
||||||
|
PCBC_MEM_CTRL = 0x05, //!< Memory controller
|
||||||
|
PCBC_BRIDGE = 0x06, //!< Bridge device
|
||||||
|
PCBC_SIMPLE_COMM = 0x07, //!< Simple communication controllers
|
||||||
|
PCBC_BASE_PERF = 0x08, //!< Base system peripherals
|
||||||
|
PCBC_INPUT = 0x09, //!< Input devices
|
||||||
|
PCBC_DOCKING = 0x0A, //!< Docking stations
|
||||||
|
PCBC_PROCESSORS = 0x0B, //!< Processors
|
||||||
|
PCBC_SERIAL_CTRL = 0x0C, //!< Serial bus controllers
|
||||||
|
PCBC_WIRELESS = 0x0D, //!< Wireless controller
|
||||||
|
PCBC_INTELLIGENT_IO = 0x0E, //!< Intelligent I/O controllers
|
||||||
|
PCBC_SATELLITE = 0x0F, //!< Satellite communication controllers
|
||||||
|
PCBC_ENCRYPT = 0x10, //!< Encryption/Decryption controllers
|
||||||
|
PCBC_SIG_PROCESS = 0x11, //!< Data acquisition and signal processing controllers
|
||||||
|
PCBC_PROC_ACCEL = 0x12, //!< Processing accelerators
|
||||||
|
PCBC_NON_ESSN = 0x13, //!< Non-Essential Instrumentation
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Mass Storage Controllers (MS)
|
||||||
|
*
|
||||||
|
* Class Code 0x01
|
||||||
|
*/
|
||||||
|
enum _PCMS
|
||||||
|
{
|
||||||
|
PCMS_SCSI = 0x00, //!< SCSI Device or Controller
|
||||||
|
PCMS_IDE = 0x01, //!< IDE Controller
|
||||||
|
PCMS_FLOPPY = 0x02, //!< Floppy Disk Controller - Vendor Specific Interface
|
||||||
|
PCMS_IPI = 0x03, //!< IPI Bus Controller - Vendor Specific Interface
|
||||||
|
PCMS_RAID = 0x04, //!< RAID Controller - Vendor Specific Interface
|
||||||
|
PCMS_ATA = 0x05, //!< ATA Controller
|
||||||
|
PCMS_SATA = 0x06, //!< SATA Controller
|
||||||
|
PCMS_SAS = 0x07, //!< SAS Controller
|
||||||
|
PCMS_NVM = 0x08, //!< Non-Volatile Memory Subsystem
|
||||||
|
PCMS_UFS = 0x09, //!< Universal Flash Storage Controller
|
||||||
|
PCMS_OTHER = 0x80 //!< Other Mass storage Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Network Controllers (NC)
|
||||||
|
*
|
||||||
|
* Class Code 0x02
|
||||||
|
*/
|
||||||
|
enum _PCNC
|
||||||
|
{
|
||||||
|
PCNC_ETH = 0x00, //!< Ethernet Controller
|
||||||
|
PCNC_TOKEN = 0x01, //!< Token Ring Controller
|
||||||
|
PCNC_FDDI = 0x02, //!< FDDI Controller
|
||||||
|
PCNC_ATM = 0x03, //!< ATM Controller
|
||||||
|
PCNC_ISDN = 0x04, //!< ISDN Controller
|
||||||
|
PCNC_WORLDFIP = 0x05, //!< WorldFip Controller
|
||||||
|
PCNC_PICMG = 0x06, //!< PICMG
|
||||||
|
PCNC_IB = 0x07, //!< InfiniBand Controller
|
||||||
|
PCNC_HFC = 0x08, //!< Host fabric Controller - Vendor Specific
|
||||||
|
PCNC_OTHER = 0x80, //!< Other Network Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Dispaly Controllers (DC)
|
||||||
|
*
|
||||||
|
* Class Code 0x03
|
||||||
|
*/
|
||||||
|
enum _PCDC
|
||||||
|
{
|
||||||
|
PCDC_VGA = 0x00, //!< VGA Compatible Controller
|
||||||
|
PCDC_XGA = 0x01, //!< XGA Controller
|
||||||
|
PCDC_3D = 0x02, //!< 3D Controller
|
||||||
|
PCDC_OTHER = 0x80, //!< Other Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Multimedia Controllers (UC)
|
||||||
|
*
|
||||||
|
* Class Code 0x04
|
||||||
|
*/
|
||||||
|
enum _PCUC
|
||||||
|
{
|
||||||
|
PCUC_VIDEO = 0x00, //!< Video Device - Vendor Specific Interface
|
||||||
|
PCUC_AUDIO = 0x01, //!< Audio Device - Vendor Specific Interface
|
||||||
|
PCUC_TELEPHONE = 0x02, //!< Computer Telephone Device - Vendor Specific Interface
|
||||||
|
PCUC_HD_AUDIO = 0x03, //!< High Definition Audio 1.0 Compatible
|
||||||
|
PCUC_OTHER = 0x80, //!< Other Multimedia device - Vendor Specific Interface
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Memory Controllers (MC)
|
||||||
|
*
|
||||||
|
* Class Code 0x05
|
||||||
|
*/
|
||||||
|
enum _PCMC
|
||||||
|
{
|
||||||
|
PCMC_RAM = 0x00, //!< RAM
|
||||||
|
PCMC_FLASH = 0x01, //!< Flash
|
||||||
|
PCMC_CXL_MEM = 0x02, //!< CXL Memory Device
|
||||||
|
PCMC_OTHER = 0x80 //!< Other
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Bridge Devices (BD)
|
||||||
|
*
|
||||||
|
* Class Code 0x06
|
||||||
|
*/
|
||||||
|
enum _PCBD
|
||||||
|
{
|
||||||
|
PCBD_HOST = 0x00, //!< Host Bridge
|
||||||
|
PCBD_ISA = 0x01, //!< ISA Bridge
|
||||||
|
PCBD_EISA = 0x02, //!< EISA
|
||||||
|
PCBD_MCA = 0x03, //!< MCA
|
||||||
|
PCBD_PPB = 0x04, //!< PCI-to-PCI Bridge
|
||||||
|
PCBD_PCMCIA = 0x05, //!< PCMCIA Bridge
|
||||||
|
PCBD_NUBUS = 0x06, //!< NuBus Bridge
|
||||||
|
PCBD_CARDBUS = 0x07, //!< CardBus Bridge
|
||||||
|
PCBD_RACEWAY = 0x08, //!< RaceWay Bridge
|
||||||
|
PCBD_STPPB = 0x09, //!< Semi-Transparent Bridge
|
||||||
|
PCBD_IB_PCI = 0x0A, //!< InfiniBand to PCI Host Bridge
|
||||||
|
PCBD_AS_PCI = 0x0B, //!< Advanced Switching to PCI Host Bridge
|
||||||
|
PCBD_OTHER = 0x80, //!< Other Bridge
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Simple communication controllers (SC)
|
||||||
|
*
|
||||||
|
* Class Code 0x07
|
||||||
|
*/
|
||||||
|
enum _PCSC
|
||||||
|
{
|
||||||
|
PCSC_GENERIC_XT = 0x00, //!< Generic XT Compatible Serial Controller
|
||||||
|
PCSC_PARALLEL = 0x01, //!< Parallel Port
|
||||||
|
PCSC_MP_SERIAL = 0x02, //!< Multi Port Serial Controller
|
||||||
|
PCSC_MODEM = 0x03, //!< Generic Modem
|
||||||
|
PCSC_GPIB = 0x04, //!< GPIB Controller
|
||||||
|
PCSC_SMRT_CARD = 0x05, //!< SMART Card
|
||||||
|
PCSC_OTHER = 0x80 //!< Other Communcations Device
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Generic System Peripherals (SP)
|
||||||
|
*
|
||||||
|
* Class Code 0x08
|
||||||
|
*/
|
||||||
|
enum _PCSP
|
||||||
|
{
|
||||||
|
PCSP_PCI = 0x00, //!< Programmable Interrupt Controller
|
||||||
|
PCSP_DMA = 0x01, //!< DMA Controller
|
||||||
|
PCSP_TIMER = 0x02, //!< System Timer
|
||||||
|
PCSP_RTC = 0x03, //!< Generic Real Time Clock (RTC) Controller
|
||||||
|
PCSP_HOT_PLUG = 0x04, //!< Generic PCI Hot Plug Contoller
|
||||||
|
PCSP_SD = 0x05, //!< SD Host Controller
|
||||||
|
PCSP_IOMMU = 0x06, //!< IOMMU
|
||||||
|
PCSP_RCEC = 0x07, //!< Root Complex Event Collector
|
||||||
|
PCSP_OTHER = 0x80, //!< Other System Peripheral
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Input Device (ID)
|
||||||
|
*
|
||||||
|
* Class Code 0x09
|
||||||
|
*/
|
||||||
|
enum _PCID
|
||||||
|
{
|
||||||
|
PCID_KEYBOARD = 0x00, //!< Keyboard Controller
|
||||||
|
PCID_PEN = 0x01, //!< Digitizer (pen)
|
||||||
|
PCID_MOUSE = 0x02, //!< Mouse Controller
|
||||||
|
PCID_SCANNER = 0x03, //!< Scanner Controller
|
||||||
|
PCID_GAME = 0x04, //!< Gameport Controller
|
||||||
|
PCID_OTHER = 0x80, //!< Other Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Docking Stations (DS)
|
||||||
|
*
|
||||||
|
* Class Code 0x0A
|
||||||
|
*/
|
||||||
|
enum _PCDS
|
||||||
|
{
|
||||||
|
PCDS_GENERIC = 0x00, //!< Generic Docking Station
|
||||||
|
PCDS_OTHER = 0x01, //!< Other type of Docking Station
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Processors (PR)
|
||||||
|
*
|
||||||
|
* Class Code 0x0B
|
||||||
|
*/
|
||||||
|
enum _PCPR
|
||||||
|
{
|
||||||
|
PCPR_386 = 0x00, //!< 386
|
||||||
|
PCPR_486 = 0x01, //!< 486
|
||||||
|
PCPR_PENTIUM = 0x02, //!< Pentium
|
||||||
|
PCPR_ALPHA = 0x10, //!< Alpha
|
||||||
|
PCPR_POWERPC = 0x20, //!< PowerPC
|
||||||
|
PCPR_MIPS = 0x30, //!< MIPS
|
||||||
|
PCPR_COPROCESSOR = 0x40, //!< Co-Processor
|
||||||
|
PCPR_OTHER = 0x80, //!< Other Processor
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Serial Bus Controllers (SB)
|
||||||
|
*
|
||||||
|
* Class Code 0x0C
|
||||||
|
*/
|
||||||
|
enum _PCSB
|
||||||
|
{
|
||||||
|
PCSB_FIREWIRE = 0x00, //!< Firewire
|
||||||
|
PCSB_ACCESS = 0x01, //!< ACCESS.bus
|
||||||
|
PCSB_SSA = 0x02, //!< SSA
|
||||||
|
PCSB_USB = 0x03, //!< USB
|
||||||
|
PCSB_FC = 0x04, //!< Fibre Channel
|
||||||
|
PCSB_SMBUS = 0x05, //!< SM Bus
|
||||||
|
PCSB_IB = 0x06, //!< Infiniband (Depricated)
|
||||||
|
PCSB_IPMI = 0x07, //!< IPMI
|
||||||
|
PCSB_SERCOS = 0x08, //!< SERCOS
|
||||||
|
PCSB_CANBUS = 0x09, //!< CANbus
|
||||||
|
PCSB_I3C = 0x0A, //!< MIPI I3C Controller
|
||||||
|
PCSB_OTHER = 0x80, //!< OTher Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Wireless Controllers (WC)
|
||||||
|
*
|
||||||
|
* Class Code 0x0D
|
||||||
|
*/
|
||||||
|
enum _PCWC
|
||||||
|
{
|
||||||
|
PCWC_IRDA = 0x00, //!< iRDA Compatible Controller
|
||||||
|
PCWC_IR = 0x01, //!< IR Controller
|
||||||
|
PCWC_RF = 0x10, //!< RF Controller
|
||||||
|
PCWC_BT = 0x11, //!< Bluetooth
|
||||||
|
PCWC_BROADBAND = 0x12, //!< Broadband
|
||||||
|
PCWC_ETH5G = 0x20, //!< Ethernet 5 GHz
|
||||||
|
PCWC_ETH2_4G = 0x21, //!< Ethernet 2.4 GHz
|
||||||
|
PCWC_CELL = 0x40, //!< Cellular Controller / Modem
|
||||||
|
PCWC_CELL_ETH = 0x41, //!< Cellular Controller + Ethrenet
|
||||||
|
PCWC_OTHER = 0x80, //!< Other Wireless Controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Intelligent IO Controllers (IO)
|
||||||
|
*
|
||||||
|
* Class Code 0x0E
|
||||||
|
*/
|
||||||
|
enum _PCIO
|
||||||
|
{
|
||||||
|
PCIO_I2O = 0x00, //!< Intelligent IO (I2O) Specification 1.0
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Satellite Controllers (SA)
|
||||||
|
*
|
||||||
|
* Class Code 0x0F
|
||||||
|
*/
|
||||||
|
enum _PCSA
|
||||||
|
{
|
||||||
|
PCSA_TV = 0x01, //!< TV
|
||||||
|
PCSA_AUDIO = 0x02, //!< Audio
|
||||||
|
PCSA_VOICE = 0x03, //!< Voice
|
||||||
|
PCSA_DATA = 0x04, //!< Data
|
||||||
|
PCSA_OTHER = 0x80, //!< Other
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Encryption Controllers (EN)
|
||||||
|
*
|
||||||
|
* Class Code 0x10
|
||||||
|
*/
|
||||||
|
enum _PCEN
|
||||||
|
{
|
||||||
|
PCEN_NET = 0x00, //!< Network and Computing Encryption Decryption controller
|
||||||
|
PCEN_ENT = 0x10, //!< Entertainment encryption and decryption controller
|
||||||
|
PCEN_OTHER = 0x80, //!< Other encryption and decryption controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Data Acquisition and Signal Processing Controllers (DA)
|
||||||
|
*
|
||||||
|
* Class Code 0x11
|
||||||
|
*/
|
||||||
|
enum _PCDA
|
||||||
|
{
|
||||||
|
PCDA_DPIO = 0x00, //!< DPIO Modules
|
||||||
|
PCDA_PERF = 0x01, //!< Performance Counters
|
||||||
|
PCDA_SYNC = 0x10, //!< Communications synchronization
|
||||||
|
PCDA_MGMT = 0x20, //!< Management Card
|
||||||
|
PCDA_OTHER = 0x80, //!< Other data acquisition controller
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Processing Accelerators (PA)
|
||||||
|
*
|
||||||
|
* Class Code 0x12
|
||||||
|
*/
|
||||||
|
enum _PCPA
|
||||||
|
{
|
||||||
|
PCPA_ACCEL = 0x00, //!< Processing Accelerator - Vendor Specific Interface
|
||||||
|
PCPA_SDXI = 0x01, //!< SNIA Smart Data Acceleration Interface (SDXI)
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Sub Class Code for Non Essential Instrumentation (NE)
|
||||||
|
*
|
||||||
|
* Class Code 0x13
|
||||||
|
*/
|
||||||
|
enum _PCNE
|
||||||
|
{
|
||||||
|
PCNE_INST = 0x00, //!< Non Essential Instrumentation - Vendor Specific Interface
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Programming Interface for Sub Class: CXL memory (CX)
|
||||||
|
*
|
||||||
|
* Class Code: 0x05
|
||||||
|
* Sub Class code 0x02
|
||||||
|
*/
|
||||||
|
enum _PCCX
|
||||||
|
{
|
||||||
|
PCCX_VS = 0x00, //!< CXL Memory Device - Vendor Specific Interface
|
||||||
|
PCCX_CXL2_0 = 0x01 //!< CXL Memory Device compliant with CXL 2.0 or later
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/* STRUCTS ===================================================================*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Capability Header
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap
|
||||||
|
{
|
||||||
|
__u8 id; //!< PCI Capability ID
|
||||||
|
__u8 next; //!< Offset of next capability. 0=end of list
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Power Management Capabilities Register (PMC)
|
||||||
|
*
|
||||||
|
* This is the first 2B of the PCI Power Management Capabilities entry
|
||||||
|
* All Read Only Fields
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap_pm_pmc
|
||||||
|
{
|
||||||
|
__u16 ver : 3; //!< Version 0x03 = complies with 1.2 of the PCI Power Mgmt Interface specification (RO)
|
||||||
|
__u16 clock : 1; //!< PME Clock Required. Always 0 for PCIe (RO)
|
||||||
|
|
||||||
|
__u16 rsvd1 : 1;
|
||||||
|
__u16 dsi : 1; //!< Device Specific Initialization is required (RO)
|
||||||
|
__u16 aux : 3; //!< Maximum AUX Current required
|
||||||
|
// 000 = 0 mA
|
||||||
|
// 001 = 55 mA
|
||||||
|
// 010 = 100 mA
|
||||||
|
// 011 = 160 mA
|
||||||
|
// 100 = 220 mA
|
||||||
|
// 101 = 270 mA
|
||||||
|
// 110 = 320 mA
|
||||||
|
// 111 = 375 mA
|
||||||
|
__u16 d1 : 1; //!< D1 Power State Supported (RO)
|
||||||
|
__u16 d2 : 1; //!< D2 Power State Supported (RO)
|
||||||
|
__u16 pme_sup : 5; //!< PME Support. Indicates the power states in which the function may assert PME# (RO)
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Power Management Control/Status Register (PMCSR)
|
||||||
|
*
|
||||||
|
* This is the 3rd and 4th bytes of the PCI Power Management Capabilities entry
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap_pm_pmcsr
|
||||||
|
{
|
||||||
|
__u16 state : 2; //!< Current Power State. Sets power state when written to (RW) 00 = D0, 01 = D1, 10 = D3, 11 = D3 hot
|
||||||
|
__u16 rsvd2 : 1; //!< Device specific. Reserved for PCIe
|
||||||
|
__u16 no_soft_rst : 1; //!< No soft Reset. When going to D0 does this device require a reset? (RO)
|
||||||
|
__u16 rsvd3 : 4;
|
||||||
|
|
||||||
|
__u16 pme_en : 1; //!< PME Enable. When set, enable power management events
|
||||||
|
__u16 data_sel : 4; //!< Data Select. Select what data is reported in last byte of pcie_cap_pm (RW)
|
||||||
|
__u16 data_scale : 2; //!< Data Scale (RO)
|
||||||
|
__u16 pme_status : 1; //!< PME Status. Shows state of PME# signal regardless if PME is enabled or not (RW)
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Bridge Support Extension Register (PMCSR_BSE)
|
||||||
|
*
|
||||||
|
* Required for all PCI-to-PCI bridges
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap_pm_bse
|
||||||
|
{
|
||||||
|
__u8 rsvd4 : 6; //!< (RO)
|
||||||
|
__u8 b2_b3 : 1; //!< Action when transitioning to D3Hot. (RO)
|
||||||
|
__u8 bpcc_en : 1; //!< Bus Power / Clock Control Enable (RO)
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Capability - Power Management
|
||||||
|
*
|
||||||
|
* ID: 0x01
|
||||||
|
* LEN: 6B
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap_pm
|
||||||
|
{
|
||||||
|
struct pcie_cap_pm_pmc pmc; //!< Power Management Capabilities Register (PMC) [2B]
|
||||||
|
struct pcie_cap_pm_pmcsr pmcsr; //!< Power Management Control/Status Register (PMCSR) [2B]
|
||||||
|
struct pcie_cap_pm_bse bse; //!< Bridge Support Extension Register (PMCSR_BSE) [1B]
|
||||||
|
__u8 data; //!< Data
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Capability - MSI Message Control
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cap_msi_ctrl
|
||||||
|
{
|
||||||
|
__u16 enable : 1; //!< MSI Enable (RW)
|
||||||
|
__u16 request : 3; //!< Requested number of vectors. 000=1, 001=2, 010=4,011=8,100=16,101=32,110=rsvd, 111=rsvd (RO)
|
||||||
|
__u16 allocated : 3; //!< Allocated number of vectors by host. (RW)
|
||||||
|
__u16 bit64 : 1; //!< 64 Bit address capable (RO)
|
||||||
|
|
||||||
|
__u16 maskable : 1; //!< Per vector masking capable. (RO)
|
||||||
|
__u16 rsvd : 7; //!<
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Extended Capability Header
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_ecap
|
||||||
|
{
|
||||||
|
__u16 id; //!< PCI Extended Capability ID
|
||||||
|
__u16 ver : 4; //!< Capability Version
|
||||||
|
__u16 next : 12; //!< Offset of next capability. 0=end of list
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Extended Capability: Device Serial Number
|
||||||
|
*
|
||||||
|
* ID: 0x0003
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_ecap_dsn
|
||||||
|
{
|
||||||
|
__u32 lo; //!< Low 4 bytes of serial number
|
||||||
|
__u32 hi; //!< Hi 4 bytes of serial number
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Header - Type field
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cfg_type
|
||||||
|
{
|
||||||
|
__u8 type : 7; //!< PCIe Header Type code
|
||||||
|
__u8 mf : 1; //!< Multi-function Device
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Header - Command Register
|
||||||
|
*
|
||||||
|
* A typical value for a modern PCIe device is
|
||||||
|
* 0x0506
|
||||||
|
* - Interupt Disable - This is 1 as devivce uses MSI
|
||||||
|
* - SERR -
|
||||||
|
* - Bus Master - Device can initiate DMA transactions
|
||||||
|
* - Mem Space - Device is accessible over PCI MemRd/Wr not PCIe IO
|
||||||
|
*
|
||||||
|
* lspic naming: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cfg_cmd
|
||||||
|
{
|
||||||
|
__u16 io : 1; //!< IO Space. If 1, dev can respond to IO space access
|
||||||
|
__u16 mem : 1; //!< Mem space. If 1, dev can respond to Memory Space access
|
||||||
|
__u16 busmaster : 1; //!< Bus Master. If 1, dev can behave as a bus master
|
||||||
|
__u16 speccycle : 1; //!< Special Cycles. If 1, dev can monitor special cycles operations
|
||||||
|
|
||||||
|
__u16 memwine : 1; //!< Memory write and invalidate enable
|
||||||
|
__u16 vgasnoop : 1; //!< VGA Palette Snoop. If 1 dev does not respond to palette register writes and will snoop the data
|
||||||
|
__u16 parerr : 1; //!< Parity Error Response. If 1 dev will take its normal action when a parity error is detected
|
||||||
|
__u16 stepping : 1; //!<
|
||||||
|
|
||||||
|
__u16 serr : 1; //!< SERR Enable. If 1 SERR# driver is enabled
|
||||||
|
__u16 fastb2b : 1; //!< Fast back to back enable
|
||||||
|
__u16 disintx : 1; //!< Interrupt Disable, If 1 the assertion of the devices INTx# signal is disabled
|
||||||
|
__u16 rsvd2 : 1;
|
||||||
|
|
||||||
|
__u16 rsvd3 : 4;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCI Header - Status Register
|
||||||
|
*
|
||||||
|
* A typical value for a modern PCIe device is
|
||||||
|
* 0x0010
|
||||||
|
* - Interupts disabled
|
||||||
|
* - Has Capabilities List
|
||||||
|
* - Only runs at 33 MHz (not 66MHz)
|
||||||
|
* - No Fast Back-to-Back transactions
|
||||||
|
* - DEVSEL = fast
|
||||||
|
*
|
||||||
|
* lspci naming: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cfg_status
|
||||||
|
{
|
||||||
|
__u16 rsvd1 : 3;
|
||||||
|
__u16 intx : 1; //!< Interrupt Status. Represents the state of the device's INTx# signal
|
||||||
|
|
||||||
|
__u16 cap : 1; //!< Capabilities List. If 1 dev implements capabilities ptr at offset 0x34; otherwise, the linked list is not available.
|
||||||
|
__u16 mhz : 1; //!< If set to 1 the device is capable of running at 66
|
||||||
|
__u16 rsvd2 : 1;
|
||||||
|
__u16 fastb2b : 1; //!< Fast Back-to-Back Capable. If 1 dev can accept fast back-to-back transactions
|
||||||
|
|
||||||
|
__u16 parerr : 1; //!< Master Data Parity Error.
|
||||||
|
__u16 devsel : 2; //!< DEVSEL Timing. RO. 0=fast, 1=medium 2=slow
|
||||||
|
__u16 sig_tabort : 1; //!< Signaled Target Abort. Set to 1 whenever a target device terminates a transaction with Target-Abort.
|
||||||
|
|
||||||
|
__u16 recv_tabort : 1; //!< Received Target Abort. Set to 1, by a master device, whenever its transaction is terminated with Target-Abort.
|
||||||
|
__u16 recv_mabort : 1; //!< Received Master Abort. Set to 1, by a master device, whenever its transaction is terminated with Master-Abort.
|
||||||
|
__u16 sig_sys_err : 1; //!< Signalled System Error. Set to 1 whenever the device asserts SERR#.
|
||||||
|
__u16 parity_err : 1; //!< Detected Parity Error. Set to 1 whenever the device detects a parity error, even if parity error handling is disabled.
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* PCIe Config Space Header
|
||||||
|
*
|
||||||
|
* The PCIe config space is 4KB and consists of:
|
||||||
|
* 1. 64 B Header
|
||||||
|
* 2. 192 B Region for PCIe Capabilities entries
|
||||||
|
* 3. 3840 B Region for PCIe Extended Capabilities entries
|
||||||
|
*/
|
||||||
|
struct __attribute__((__packed__)) pcie_cfg_hdr
|
||||||
|
{
|
||||||
|
__u16 vendor; //!< Vendor ID
|
||||||
|
__u16 device; //!< Device ID
|
||||||
|
__u16 command; //!< Command register
|
||||||
|
__u16 status; //!< Status register
|
||||||
|
__u8 rev; //!< Class Revision ID
|
||||||
|
__u8 pi; //!< Programming Interface
|
||||||
|
__u8 subclass; //!< Sub Class Code
|
||||||
|
__u8 baseclass; //!< Base Class Code
|
||||||
|
__u8 cls; //!< Cache Line Size
|
||||||
|
__u8 timer; //!< PCIe Latency Timer
|
||||||
|
__u8 type; //!< 0 = Endpoint, 1 = Switch, 2 = cardbus
|
||||||
|
__u8 bist; //!< Capable & Start bits
|
||||||
|
__u32 bar0; //!< Base Address Register 0
|
||||||
|
__u32 bar1; //!< Base Address Register 1
|
||||||
|
__u32 bar2; //!< Base Address Register 2
|
||||||
|
__u32 bar3; //!< Base Address Register 3
|
||||||
|
__u32 bar4; //!< Base Address Register 4
|
||||||
|
__u32 bar5; //!< Base Address Register 5
|
||||||
|
__u32 cis; //!< Cardbud CIS pointer
|
||||||
|
__u16 subvendor; //!< Subsystem Vendor ID
|
||||||
|
__u16 subsystem; //!< Subsystem ID
|
||||||
|
__u32 rom; //!< Expansion ROM Base Address
|
||||||
|
__u8 cap; //!< Capability List Offset to first entry
|
||||||
|
__u32 rsvd : 24;
|
||||||
|
__u32 rsvd2;
|
||||||
|
__u8 intline; //!< Interrupt line
|
||||||
|
__u8 intpin; //!< Interrupt pin
|
||||||
|
__u8 mingnt; //!< Minimum grant for burst period length in 1/4 microsecond units assuming 33MHz clock
|
||||||
|
__u8 maxlat; //!< Maximum LAtency
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/* PROTOTYPES ================================================================*/
|
||||||
|
|
||||||
|
const char *pcap(unsigned u);
|
||||||
|
const char *pcec(unsigned u);
|
||||||
|
const char *pccx(unsigned u);
|
||||||
|
const char *pcmc(unsigned u);
|
||||||
|
const char *pcms(unsigned u);
|
||||||
|
const char *pcnc(unsigned u);
|
||||||
|
const char *pcdc(unsigned u);
|
||||||
|
const char *pcuc(unsigned u);
|
||||||
|
const char *pcbd(unsigned u);
|
||||||
|
const char *pcsc(unsigned u);
|
||||||
|
const char *pcsp(unsigned u);
|
||||||
|
const char *pcid(unsigned u);
|
||||||
|
const char *pcds(unsigned u);
|
||||||
|
const char *pcpr(unsigned u);
|
||||||
|
const char *pcsb(unsigned u);
|
||||||
|
const char *pcwc(unsigned u);
|
||||||
|
const char *pcio(unsigned u);
|
||||||
|
const char *pcsa(unsigned u);
|
||||||
|
const char *pcen(unsigned u);
|
||||||
|
const char *pcda(unsigned u);
|
||||||
|
const char *pcpa(unsigned u);
|
||||||
|
const char *pcne(unsigned u);
|
||||||
|
|
||||||
|
void pcie_prnt_cfgspace(__u8 *cfgspace, unsigned indent);
|
||||||
|
|
||||||
|
/* GLOBAL VARIABLES ==========================================================*/
|
||||||
|
|
||||||
|
#endif //ifndef _PCIE_H
|
||||||
Loading…
Reference in New Issue
Block a user