245 lines
8.3 KiB
C
245 lines
8.3 KiB
C
/* SPDX-License-Identifier: Apache-2.0 */
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/**
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* @file cxlstate.h
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*
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* @brief Header file for CXL State library
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*
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* @copyright Copyright (C) 2024 Jackrabbit Founders LLC. All rights reserved.
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*
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* @date Mar 2024
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* @author Barrett Edwards <code@jrlabs.io>
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*
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*/
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#ifndef _CXLSTATE_H
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#define _CXLSTATE_H
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/* INCLUDES ==================================================================*/
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/* pthread_mutex_t
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*/
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#include <pthread.h>
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#include <linux/types.h>
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/* MACROS ====================================================================*/
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#define CXLN_LD 16
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#define CXLN_PORTS 256
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#define CXLN_VCSS 256
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#define CXLN_VPPBS_PER_VCS 256
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#define CXLN_VPPBS (CXLN_PORTS * CXLN_LD)
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#define CXLN_DEVICES 128
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#define CXLN_MAX_INDENT 32
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#define CXLN_INDENT 2
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#define CXLN_CFG_SPACE 4096
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#define CXLN_FILE_NAME 256
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/* ENUMERATIONS ==============================================================*/
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/**
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* CXLS Verbosity Bit Field (VB)
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*/
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enum _CXVB
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{
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CXVB_GENERAL = (0x01 << 0),
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CXVB_CALLSTACK = (0x01 << 1),
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CXVB_STEPS = (0x01 << 2)
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};
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/* STRUCTS ===================================================================*/
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/**
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* Multi Logical Device Object*
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*
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* This device aggregates all the descriptors for a CXL MLD Logical Device
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*
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* CXL 2.0 v1.0 Table 111,112,113,116,117,118,119
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*/
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struct cxl_mld
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{
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/* LD Info: Table 111*/
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__u64 memory_size; //!< Total device memory capacity
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__u16 num; //!< Number of Logical Devices supported
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__u8 epc; //!< Egress Port Congestion Supported
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__u8 ttr; //!< Temporary Throughput Reduction Supported
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/* LD Allocations: Table 112,113 */
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__u8 granularity; //!< Memory Granularity [FMMG]
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__u64 rng1[CXLN_LD]; //!< Range 1 Allocation Multiplier
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__u64 rng2[CXLN_LD]; //!< Range 2 Allocation Multiplier
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/* LD QoS Control parameters: Table 116*/
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__u8 epc_en; //!< QoS Telem: Egress Port Congestion Enable. Bitfield [FMQT]
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__u8 ttr_en; //!< QoS Telem: Temporary Throuhput Reduction Enable. Bitfield [FMQT]
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__u8 egress_mod_pcnt; //!< Egress Moderate Percentage: Valid range 1-100. Default 10
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__u8 egress_sev_pcnt; //!< Egress Severe Percentage: Valid range 1-100. Default 25
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__u8 sample_interval; //!< Backpressure Sample Interval: Valid range is 0-15. Default 8 (800 ns of history). 0 disables
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__u16 rcb; //!< ReqCmpBasis. Valid range is 0-65,535. 0 disables. Default 0.
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__u8 comp_interval; //!< Completion Collection Interval: Valid range 0-255. Default 64
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/* LD QoS Status: Table 117*/
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__u8 bp_avg_pcnt; //!< Backpressure Average Percentage
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/* LD QoS Allocated BW Fractions: Table 118 */
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__u8 alloc_bw[CXLN_LD];
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/* LD QoS BW Limit Fractions: Table 119 */
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__u8 bw_limit[CXLN_LD];
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__u8 *cfgspace[CXLN_LD]; //!< Buffers representing PCIe config space for each logical device
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__u8 mmap; //!< Direction to mmap a file for the memory space
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char *file; //!< Filename for mmaped file
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__u8 *memspace; //!< Buffer representing memory space for entire logical device
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};
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/**
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* Virtual PCIe-to-PCIe Bridge Object
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*
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* CXL 2.0 v1.0 Table 99
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*/
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struct cxl_vppb
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{
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__u16 vppbid; //!< Index of this vPPB in the state->vppbs[] array
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__u8 bind_status; //!< PBB Binding Status [FMBS]
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__u8 ppid; //!< Physical port number of bound port
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__u16 ldid; //!< ID of LD bound to port from MLD on associated physical port
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};
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/**
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* Virtual CXL Switch Object
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*
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* CXL 2.0 v1.0 Table 99
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*/
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struct cxl_vcs
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{
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__u8 vcsid; //!< VCS ID - Index of this vcs in the state->vcss[] array
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__u8 state; //!< Virtual CXL switch State [FMVS]
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__u8 uspid; //!< USP Physical Port ID
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__u8 num; //!< Number of vPPBs
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//!< Array of pointers to vPPB objects
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struct cxl_vppb vppbs[CXLN_VPPBS_PER_VCS];
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};
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/**
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* CXL Switch Port Object
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*
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* CXL 2.0 v1.0 Table 92
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*/
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struct cxl_port
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{
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__u8 ppid; //!< Port ID - Index of this port in the state->ports[] array
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__u8 state; //!< Current Port Configuration State [FMPS]
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__u8 dv; //!< Connected Device CXL version [FMDV]
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__u8 dt; //!< Connected device type [FMDT]
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__u8 cv; //!< Connected CXL version bitmask [FMVC]
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__u8 mlw; //!< Max Link Width. Integer number of lanes (1,2,4,8,16)
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__u8 nlw; //!< Negotiated Link Width [FMNW]
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__u8 speeds; //!< Supported Link Speeds Vector [FMSS]
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__u8 mls; //!< Maximum Link Speed [FMMS]
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__u8 cls; //!< Current Link Speed [FMMS]
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__u8 ltssm; //!< LTSSM State [FMLS]
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__u8 lane; //!< First negotiated lane number (Integer lane number)
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/** Link State Flags [FMLF] [FMLO] */
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__u8 lane_rev; //!< Lane reversal state. 0=standard, 1=rev [FMLO]
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__u8 perst; //!< PCIe Reset State PERST#
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__u8 prsnt; //!< Port Presence pin state PRSNT#
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__u8 pwrctrl; //!< Power Control State (PWR_CTRL)
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__u8 ld; //!< Additional supported LD Count (beyond 1)
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__u8 *cfgspace; //!< Buffer representing PCIe config space
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struct cxl_mld *mld; //!< State for MLD
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char *device_name; //!< Name of device used to populate this port
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};
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/**
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* CXL Device Profile
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*/
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struct cxl_device
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{
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char *name; //!< Name of device
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__u8 rootport; //!< Root Port Device. 1=root, 2=endpoint
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__u8 dv; //!< Connected Device CXL version [FMDV]
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__u8 dt; //!< Connected device type [FMDT]
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__u8 cv; //!< Connected CXL version bitmask [FMVC]
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__u8 mlw; //!< Maximum Link Width. Integer number of lanes (1,2,4,8,16)
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__u8 mls; //!< Maximum Link Speed [FMMS]
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__u8 *cfgspace; //!< Buffer representing PCIe config space
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struct cxl_mld *mld; //!< MLD info if this is an MLD
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};
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/**
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* CXL Switch State Identify Information
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*
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* CXL 2.0 v1 Table 89
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*/
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struct cxl_switch
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{
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__u8 version; //!< Device Management Version
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__u16 vid; //!< PCIe Vendor ID
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__u16 did; //!< PCIe Device ID
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__u16 svid; //!< PCIe Subsystem Vendor ID
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__u16 ssid; //!< PCIe Subsystem ID
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__u64 sn; //!< Device Serial Number
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__u8 max_msg_size_n; //!< Max fmapi msg size. 2^n
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__u8 msg_rsp_limit_n; //!< Message Response Limit n of 2^n
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__u8 bos_running; //!< Background operation status 0=none, 1=running
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__u8 bos_pcnt; //!< Background operation percent complete [0-100]
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__u16 bos_opcode; //!< Background operation opcode
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__u16 bos_rc; //!< Background operation return code
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__u16 bos_ext; //!< Background operation Extended Vendor Status
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__u8 ingress_port; //!< Ingress Port ID
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__u8 num_ports; //!< Total number of physical ports
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__u8 num_vcss; //!< Max number of VCSs
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__u16 num_vppbs; //!< Max number of vPPBs
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__u16 active_vppbs; //!< Number of active vPPBs
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__u8 num_decoders; //!< Number of HDM decoders available per USP
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struct cxl_port *ports; //!< array of Port objects
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struct cxl_vcs *vcss; //!< array of VCS objects
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struct cxl_device *devices; //!< array of device definitions
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__u16 len_devices; //!< Number of entries supported in devices array
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__u16 num_devices; //!< Number of entries in devices array
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/* Port defaults */
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__u8 mlw; //!< Max Link Width. Integer number of lanes (1,2,4,8,16)
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__u8 speeds; //!< Supported Link Speeds Vector [FMSS]
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__u8 mls; //!< Maximum Link Speed [FMMS]
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char *dir; //!< Filepath to directory for instantiated memory
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pthread_mutex_t mtx; //!< Mutex to control access to this object
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};
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/* GLOBAL VARIABLES ==========================================================*/
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extern __u64 cxls_verbosity;
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/* PROTOTYPES ================================================================*/
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struct cxl_switch *cxls_init(unsigned ports, unsigned vcss, unsigned vppbs);
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void cxls_free (struct cxl_switch *s);
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int cxls_connect (struct cxl_port *p, struct cxl_device *d, char *dir);
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int cxls_disconnect (struct cxl_port *p);
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void cxls_prnt (struct cxl_switch *s);
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void cxls_prnt_identity (struct cxl_switch *s, unsigned indent);
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void cxls_prnt_devices (struct cxl_switch *s);
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void cxls_prnt_ports (struct cxl_switch *s, unsigned indent);
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void cxls_prnt_port (struct cxl_port *p, unsigned indent);
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void cxls_prnt_vcss (struct cxl_switch *s, unsigned indent);
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void cxls_prnt_vcs (struct cxl_vcs *v, unsigned indent);
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void cxls_prnt_vppb (struct cxl_vppb *b, unsigned indent);
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void cxls_prnt_mld (struct cxl_mld *m, unsigned indent);
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#endif /* ifndef _CXLSTATE_H */
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